A configurable Mu itiprocessor and dynamic load balancing for parallel LU factorization

Document Type

Conference Proceeding

Publication Date

12-1-2004

Abstract

The exponentially increasing complexity of many scientific applications and the high cost of supercomputing force us to explore new, sustainable, and affordable high-performance computing platforms. Recent significant advances in FPGA technology and the inherent advantages of configurable logic have brought about new research efforts in the configurable computing field: parallel processing on configurable chips. We explore here parallel LU factorization of large sparse block-diagonal-bordered (BDB) matrices on a configurable multiprocessor that we have designed and implemented. A dynamic load balancing strategy is proposed and analyzed. Performance results for IEEE power test systems are provided. Our research provides evidence that configurable logic can be a viable alternative to high-performance scientific computing.

Identifier

12444286785 (Scopus)

ISBN

[0769521320, 9780769521329]

Publication Title

Proceedings International Parallel and Distributed Processing Symposium IPDPS 2004 Abstracts and Cd Rom

First Page

3231

Last Page

3238

Volume

18

This document is currently not available here.

Share

COinS