HERA: A reconfigurable and mixed-mode parallel computing engine on platform FPGAs

Document Type

Conference Proceeding

Publication Date

12-1-2004

Abstract

The high price, long design and development cycles, programming difficulty and high maintenance cost of supercomputers limit their range of potential applications. Recent advances in Field-Programmable Gate Arrays (FPGAs) have made feasible the development of high-performance and programmable parallel systems on a programmable chip (PSOPC). PSOPC's yield high-performance at low cost for many parallel applications. We present in this paper the design and implementation of our HERA (HEterogeneous Reconfigurable Architecture) machine that employs FPGAs to allow the simultaneous execution of a variety of parallel processing modes, including SIMD (Single-Instruction, Multiple-Data), MIMD (Multiple-Instruction, Multiple-Data) and M-SIMD (Multiple-SIMD). The processing element is centered on a single-precision IEEE 754 floating-point unit (FPU) and employs a 7-stage pipeline. To demonstrate the robustness and viability of our approach, we propose a data partitioning scheme and employ mixed-mode scheduling for Cannon's matrix-matrix multiplication algorithm with matrices of arbitrary size and shape. Performance results on our 64-PE machine that employs a dual-FPGA system are better than the optimized performance on a dual-Xeon PC.

Identifier

11844292749 (Scopus)

Publication Title

Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems

ISSN

10272658

First Page

374

Last Page

379

Volume

16

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