Memory chip BIST architecture

Document Type

Conference Proceeding

Publication Date

12-1-1999

Abstract

A unique testable design for random access memory (RAM) is presented. The design uses linear feedback shift registers and a comparator to assist the test. These test aids can be placed on or off product, depending upon the design constraints. The proposed testable design offers many benefits in terms of simplicity, modularity, fault coverage, and fault diagnosis.

Identifier

0033355867 (Scopus)

ISBN

[0769501044]

Publication Title

Proceedings of the IEEE Great Lakes Symposium on VLSI

ISSN

10661395

First Page

384

Last Page

385

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