RAM BIST

Document Type

Article

Publication Date

1-1-2001

Abstract

A random access memory (RAM) testable design for both testing and diagnosis was presented. The testable design used linear feedback shift registers and a comparator to assist the built-in self-test (BIST). The test required only random data, hence the test length needed to be carefully assessed. The test length required to detect RAM faults depended on which faults are targeted. Hardware overhead for the test was very low and decreased with the increase in the size of the array.

Identifier

0035111718 (Scopus)

Publication Title

IEICE Transactions on Electronics

ISSN

09168524

First Page

102

Last Page

107

Issue

1

Volume

E84-C

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