A low jitter CMOS PLL clock synthesizer with 20-400 MHz locking range
Document Type
Conference Proceeding
Publication Date
1-1-2007
Abstract
This paper describes the design of a CMOS PLL clock synthesizer targeting biomedical applications in the 20-400 MHz range. Based on an integer-N architecture, the synthesizer produces a 400-mV LVDS output signal swing on a 1.2 V common mode level under 50-Ω load. Fabricated in a 0.35-μm N-well CMOS process technology, the PLL achieves a period jitter of 6.5-ps rms and 38-pspP at 216 MHz with a phase noise of -120 dBc/Hz at frequency offsets above 10 KHz. The phase noise response has a peak of -115 dBc/Hz at the loop bandwidth. © 2007 IEEE.
Identifier
34548822448 (Scopus)
Publication Title
Proceedings IEEE International Symposium on Circuits and Systems
External Full Text Location
https://doi.org/10.1109/iscas.2007.378067
ISSN
02714310
First Page
3111
Last Page
3114
Recommended Citation
Gundel, Adnan and Carr, William N., "A low jitter CMOS PLL clock synthesizer with 20-400 MHz locking range" (2007). Faculty Publications. 13706.
https://digitalcommons.njit.edu/fac_pubs/13706
