FPGA-based vector processing for matrix operations
Document Type
Conference Proceeding
Publication Date
8-28-2007
Abstract
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 single-precision floating-point standard and also the efficient implementation of some sparse matrix operations. The processor is implemented on the Xilinx XC2V6000-5 FPGA chip. To test the performance, the W-matrix sparse solver for linear equations is realized. W-matrix was first proposed for power flow analysis and is prone to parallel computing. We show that actual power matrices with up to 1723 nodes can be dealt with in less than 1.1ms on the FPGA. A comparison with a commercial PC indicates that the vector processor is competitive for such computation-intensive problems. © 2007 IEEE.
Identifier
34548138017 (Scopus)
ISBN
[0769527760, 9780769527765]
Publication Title
Proceedings International Conference on Information Technology New Generations Itng 2007
External Full Text Location
https://doi.org/10.1109/ITNG.2007.95
First Page
989
Last Page
994
Recommended Citation
Hongyan, Yang; Ziavras, Sotirios G.; and Jie, Hu, "FPGA-based vector processing for matrix operations" (2007). Faculty Publications. 13341.
https://digitalcommons.njit.edu/fac_pubs/13341
