Vector processing support for FPGA-oriented high performance applications

Document Type

Conference Proceeding

Publication Date

11-28-2007

Abstract

In this paper, we propose and implement a vector processing system that includes two identical vector microprocessors embedded in two FPGA chips. Each vector microprocessor supports floating-point calculations and efficient sparse matrix operations. Dense matrix-matrix multiplication and sparse matrix-vector multiplication with benchmark matrices from various application domains were run on the system to evaluate its performance. The resulting calculation times are compared with those of a commercial PC to show the effectiveness of our approach. © 2007 IEEE.

Identifier

36349022540 (Scopus)

ISBN

[0769528961, 9780769528960]

Publication Title

Proceedings IEEE Computer Society Annual Symposium on VLSI Emerging VLSI Technologies and Architectures

External Full Text Location

https://doi.org/10.1109/ISVLSI.2007.100

First Page

447

Last Page

448

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