Breakdown characteristics of high-K gate dielectrics with metal gates

Document Type

Conference Proceeding

Publication Date

11-17-2008

Abstract

Considering the breakdown mechanisms of high-k and interfacial (IL) layers are different at higher temperatures than at room temperature, in this work the temperature dependence of stress induced leakage current (SILC) and time dependent dielectric breakdown (TDDB) of theses layers are studied separately. As observed from the low voltage SILC, the interfacial layer initiates the gate stack breakdown process at elevated temperature which is followed by the high-k layer. Activation energy extracted from Weibulll distribution of time-to-breakdown (TBD) data from high-k layer further suggests that the gate stack breakdown occurs when high-k layer ultimately breaks down. © The Electrochemical Society.

Identifier

55849126698 (Scopus)

ISBN

[9781566776271]

Publication Title

Ecs Transactions

External Full Text Location

https://doi.org/10.1149/1.2908621

e-ISSN

19386737

ISSN

19385862

First Page

91

Last Page

97

Issue

2

Volume

13

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