Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-26-2023
Description
Figure 7.21: 4-bit synchronous upcounter. Initially the output is 0111. When CLK changes from 0 to 1, the output changes to 1000. When CLK changes back to 0 and back to 1 again, the output changes to 1001.
Recommended Citation
Carpinelli, John D., "Figure 7.21: 4-bit synchronous upcounter." (2023). An Animated Introduction to Digital Logic Design - Animations. 97.
https://digitalcommons.njit.edu/dld-animations/97
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
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