Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-26-2023
Description
Figure 6.20: J-K flip-flop: Leader-follower design. The circuit has two S-R latches. Input S of the first latch is connected to the output of a 3-input AND gate with inputs J, CLK passed through a NOT gate, and output Q' of the second latch. Input R of the first latch is connected to the output of a 3-input AND gate with inputs K, CLK passed through a NOT gate, and output Q of the second latch. Input S of the second latch is connected to the output of a 2-input AND gate with inputs Q of the first latch and CLK. Input R of the second latch is connected to a 2-input AND gate with inputs Q' of the first latch and CLK. Output Q of the second latch is labeled Q and output Q' of the second latch is labeled Q'. Initially, J=K=CLK=0, the inputs to both latches are 0, and the outputs of both latches are Q=0 and Q'=1. CLK changes to 1 and the R input of the second latch changes to 1. Then CLK changes to 0 and the R input of the second latch changes to 0. Next, J and K both change to 1, input S of the first latch changes to 1, and output Q of the first latch changes to 1. Then CLK changes to 1, input S of the first latch changes to 1, input S of the second latch changes to 1, and the outputs of the second latch change to Q=1 and Q'=0. Next, CLK changes to 0, input S of the first latch changes to 0, input Q of the first latch changes to 1, the outputs of the first latch change to Q=0 and Q'=1, and input S of the second latch changes to 0. Input J changes to 0 and all other signal remain unchanged. CLK changes to 1. Input R of the first latch changes to 0 and input R of the second latch changes to 1; the outputs of the second latch change to Q=0 and Q'=1. CLK changes to 0 and input R of the second latch changes to 0. Input J changes to 1 and input K changes to 0. This sets input S of the first latch to 1, input R of the first latch to 0, and the outputs of the first latch to Q=1 and Q'=0. Then CLK changes to 1. Input S of the first latch changes to 0. Input S of the second latch changes to 1 and the outputs of the second latch to Q=1 and Q'=0. Next, CLK changes to 0 and input S of the second latch changes to 0. K changes to 1, input R of the first latch changes to 1, and the outputs of the first latch change to Q=0 and Q'=1. CLK changes to 1 and input R of the first latch changes to 0, input R of the second latch changes to 1, and the outputs of the second latch change to Q=0 and Q'=1. Finally, CLK changes to 0 and input S of the first latch changes to 1, the outputs of the first latch change to Q=1 and Q'=0, and input R of the second latch changes to 1.
Recommended Citation
Carpinelli, John D., "Figure 6.20: J-K flip-flop: Leader-follower design." (2023). An Animated Introduction to Digital Logic Design - Animations. 85.
https://digitalcommons.njit.edu/dld-animations/85
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