Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-26-2023
Description
Figure 6.16: D flip-flop: (a) Leader-follower design; (b) Signal values for sample input sequence. The animation shows the timing diagram and the circuit, with the values of each signal and the portion of the timing diagram being realized shown in red. Initially, D and CLK are 0, output Q of the first latch is 0, output Q of the second latch is 0, and output Q' of the second latch is 1. Then D changes to 1. Output Q of the first latch changes to 1. CLK changes to 1 and the outputs of the second latch change to Q=1 and Q'=0. Next, D changes to 0 and then back to 1 and back to 0 again; no other signals change their values. CLK then changes to 0, and output Q of the first latch changes to 0. D changes to 1 and back to 0. Output Q of the first latch changes to 1 and 0 at the same time as D, and no other signals change their values. Next, CLK changes to 1 and the outputs of the second latch change to Q=0 and Q'=1.
Recommended Citation
Carpinelli, John D., "Figure 6.16: D flip-flop: (a) Leader-follower design; (b) Signal values for sample input sequence." (2023). An Animated Introduction to Digital Logic Design - Animations. 83.
https://digitalcommons.njit.edu/dld-animations/83
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
