Author ORCID Identifier
0000-0003-3621-0168
Document Type
Animation
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Publication Date
6-26-2023
Description
Figure 10.9: D flip-flop model of a 16x2 ROM with chip enable and output enable signals. The animation shows the asserted signals and data for A3-A2-A1-A0 = 0-1-0-0.
Recommended Citation
Carpinelli, John D., "Figure 10.9: D flip-flop model of a 16x2 ROM with chip enable and output enable signals." (2023). An Animated Introduction to Digital Logic Design - Animations. 129.
https://digitalcommons.njit.edu/dld-animations/129
Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial-Share Alike 4.0 International License.
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