Document Type


Date of Award

Fall 1-31-2001

Degree Name

Master of Science in Electrical Engineering - (M.S.)


Electrical and Computer Engineering

First Advisor

Nirwan Ansari

Second Advisor

Jianguo Chen

Third Advisor

John D. Carpinelli


Scheduling algorithms are implemented in hardware in high-speed switches to provide Quality-of-Service guarantees in both cell-based and packet-based networks. Being able to guarantee end-to-delay and fairness, timestamp-based fair queuing algorithms, which include SCFQ, WFQ, WF2Q and WF2Q+, have received much attention in the past few years. In timestamp-based fair queuing algorithms, the size of timestamp and period determines the supportable rates in terms of the range and accuracy. Furthermore, it also determines the scheduler's memory in terms of offchip bandwidth and storage space. An efficient expression can reduce the size of the timestamp and period without compromising the accuracy. In this thesis, we propose a new expression for the timestamp and period, which can be implemented in hardware for both high-speed packet-based and cell-based switches. As compared to fixed-point and floating-point number expressions, when the size is fixed, the proposed expression has a better accuracy.



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