Date of Award

Summer 2003

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

Durgamadhab Misra

Second Advisor

William N. Carr

Third Advisor

Kenneth Sohn

Abstract

With continued scaling of MOSFET's, the reliability of thin gate oxides is becoming increasingly important. Degradation issues due to fabrication technology may result in misinterpretation unless the actual physical situation arising at source, drain, gate and substrate of a transistor during processing is understood. This degradation is prominent in plasma processing due to wafer charging which occurs due to the reactive ions in the plasma. The voltages developed at source and drain junctions, depending upon polarity relative to the substrate cause the source and drain junctions to be forward biased or reverse biased. Keeping in view this type of physical situation arising at the source and drain junctions, this thesis reports the effects of reverse biased potential at source and drain junctions of a nMOSFET during high-field substrate injection and its impact on device parameters such as transconductance, threshold voltage and hot carrier degradation.

For the present study n-MOS transistors processed using 0.25 uμ technologywere used for study. Transistors were subjected to about 400mAIcm constant current stress for three seconds using substrate injection mode, while applying potential at the

source and drain to simulate reverse bias condition created by plasma charging. While applying potential at the source and drain, hot carrier lifetime based on 10% threshold voltage and transconductance degradation of the transistors were measured.

Experimentally it was observed that threshold voltage prior to stress was lower than threshold voltage after stress indicating dominant electron trapping. Since the device is in strong inversion during stress, an increase in reverse biased voltage at the source and drain, will form the channel in the center of the device due to the depletion regions of source and drain junctions. Results show the hot carrier lifetime based on transconductance shift decreases after current stress. It shows an improvement when the reverse bias is at lV and further degrades when reverse bias increases to 2V. These results clearly indicate that the source - drain depletion regions formed by reverse bias affect hot carrier lifetime.

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