Document Type

Thesis

Date of Award

5-31-1988

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical Engineering

First Advisor

John D. Carpinelli

Second Advisor

Michael Pratap Singh

Abstract

This study is aimed at the development of an interactive PC-based package for simulating data flow within an arithmetic pipeline in multiprocessor systems. The user constructs the arithmetic pipeline, specifying the functionality of each segment, the intersegment connectivity and pipeline inputs and outputs. After defining reservation tables and data, analysis is performed with the results available in tabular, simple graphic and animated graphic forms.

APAP allows the user to design hardware and analyze its functionality with-out building the circuit, an economical alternative. Even when circuits are to be built, APAP allows the user to correct logic errors before implementation, leaving only timing and wiring errors to be resolved. Feedback from its use in graduate classes is used to define optimal applications for students in both the graduate and undergraduate curricula.

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