Electrical measurements of MOS structures fabricated on etched silicon surfaces

Author

Venkata Ramana Vankayalapati, New Jersey Institute of Technology

Document Type

Thesis

Date of Award

12-31-1990

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

N. M. Ravindra

Second Advisor

Kenneth Sohn

Third Advisor

Durgamadhab Misra

Abstract

This thesis details the electrical characterization of thermally grown thin SiO₂ films on virgin and plasma etched silicon surfaces. The electrical characterization techniques employed for the present study are high frequency Capacitance Voltage(C-V) and Current-Voltage(I-V) measurements. The structures used in this study are Al/Polysilicon/SiO₂/Si/A1 capacitors fabricated on n-Si and p-Si substrates. These capacitors with areas in the range of 0.001-0.05 cm₂, were made using various plasma process conditions and etch reactors.

Based on the experimental results of the C-V anlaysis, in comparison of the controls samples with the plasma treated samples, we could not see significant changes in the values of the C-V parameters. This may be due to the fact that silicon has seen the plasma and oxide has not seen the plasma. Further, the etched silicon has been subsequently exposed to several high temperature processes including thermal oxidation, LPCVD and post-metal anneal.

For the I-V analysis, we have used static and dynamic or TDDB measurements.

Recommended Citation

Vankayalapati, Venkata Ramana, "Electrical measurements of MOS structures fabricated on etched silicon surfaces" (1990). Theses. 2981.
https://digitalcommons.njit.edu/theses/2981