Document Type
Thesis
Date of Award
9-30-1990
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Durgamadhab Misra
Second Advisor
N. M. Ravindra
Third Advisor
William N. Carr
Abstract
Schottky barrier MOSFETs are expected to offer certain fabrication advantages, low series resistance and the feasibility to go into sub-micron technology without having short-channel effects. A p-channel MOSFET using Schottky contacts as source and drain is reviewed theoritically. The limitations of the device arising from the oxide offset between source/channel is studied with the help of one dimensional simulation SEDAN. The process sequence leads to an offset between source and channel. The performance of the SBMOSFETs with and without offset is estimated using two dimensional device simulation program PISCES-II for PtSi and IrSi as source and drain material. A novel process sequence is proposed to eliminate the oxide separation(offset), which is responsible for the degradation in device performance between source/drain and channel of SBMOSFET. The modified device structure without offset (gate overlapping source/drain edges) is simulated to estimate its performance. The gain of SBMOSFET with overlapping gate using PtSi is 32% and using IrSi is 82% of the conventional MOSFET's gain ( from PISCES simulations).
Recommended Citation
Simhadri, Venkata S., "A novel Schottky barrier MOSFET for VLSI applications" (1990). Theses. 2924.
https://digitalcommons.njit.edu/theses/2924
