Document Type
Thesis
Date of Award
1-31-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Durgamadhab Misra
Third Advisor
Yunjin Kim
Abstract
This thesis describes the design of a CMOS digital temperature sensor cell including the physical layout database.This cell is designed for implementation within an ASIC VLSI chip as a standard cell . The digital temperature sensor can trigger an alarm signal and turn off power for preventing fatal damage in the VLSI chip if overheating occurs.A digital output also permits measurement of temperature over the 0 - 120°C range with ±3.4°C accuracy using standard VLSI foundry processing. Two sensing elements are implemented in a differential mode within the temperature sensor cell. An operational amplifier is used in the successive approximation ADC as a comparator. The level shifter is also used for voltage summation in the ADC design. The error due to simulated device temperature dependence, and power supply voltage ±10% swing are ±1.40% 1.68°C) and ±1.41% ( 1.69°C) respectively over the 0 - 120°C range. This CMOS digital temperature sensor cell measures 48mi1 x 55mi1 using MOSIS 3μ CMOS layout rules for single level metal and single level polysilicon. The calculated analog power dissipation is 15mW. The digital circuits dissipate 0.2mW per MHz clock. This circuit is simulated by using UC Berkeley SPICE 2(4.5 and designed using Mentor Graphics Corporation tools.
Recommended Citation
Sung, Chih-Ta, "A CMOS digital temperature sensor for ASIC VLSI standard cell design" (1989). Theses. 2912.
https://digitalcommons.njit.edu/theses/2912
