Document Type


Date of Award


Degree Name

Master of Science in Electrical Engineering - (M.S.)


Electrical and Computer Engineering

First Advisor

Durgamadhab Misra

Second Advisor

N. M. Ravindra

Third Advisor

Kenneth Sohn


A new C-MOS NAND and CMOS full adder logic circuits which reduces hot carrier problems are discussed. The application of new circuit lowers the channel electric field in N-MOSFET during switching transient and leads to suppression of the N-MOSFET substrate current. The simulation results shows that about 3.99 and 3.75 times smaller peak substrate current are obtained in C-MOS NAND and adder with new circuit compared to the conventional logic circuits. These logic circuits also gives better noise and shows shorter rise and fall times. The new concept provides highly reliable logic circuits without any change of device structure or fabrication process.



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