Document Type


Date of Award


Degree Name

Master of Science in Electrical Engineering - (M.S.)


Electrical and Computer Engineering

First Advisor

Sotirios Ziavras

Second Advisor

John D. Carpinelli

Third Advisor

Yun Q. Shi


Algorithms for fast arithmetic operations (i.e., addition and multiplication) on the hypercube computer are presented. The hypercube network of dimension d interconnects N = 2d processors in such a way that each processor is directly connected to d neighboring processors; m order to communicate between processors, the maximum length of the path is d. The addition algorithm is based on the conditional sum technique. The computational time using this algorithm is O(log2 N+q) where q is the number of the bits per processor in the hypercube of N processors. Operands of size N*q are distributed among the hypercube processors using high-order interleaving Only two hits ate exchanged in every cycle of communication for a total of log2 N communication cycles. A modified version of Booth's algorithm is adopted for fast multiplication and generates Fn/2 I partial products, where the size of the multiplier is 11 bits. These 1?n/21 partial products are half of those required by conventional multiplication. Each processor of the hypercube generates I?n/2N1 partial products, simultaneously. These partial products are distributed among the N processors using high-order interleaving. Each processor contains I (n+ni )/N I bits, where n and in are the numbers of bits in the multiplier and the multiplicand respectively. A carry-save addition (CSA) technique is used to add these multiple partial product. These multiple partial products are reduced to two operands (i.e., carry and sum) in (1n/21 - 2) iterations, which are finally added using the algorithm described earlier. The time taken by the multiplication process is O(log2 N(nq+1) + n(q+1 +1 IN) - q). These algorithm are .imulated and comparative analysis is performed for various sizes of operands and hypercube,, of various dimensions.



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