Document Type

Thesis

Date of Award

10-31-1993

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

Ali N. Akansu

Second Advisor

Yeheskel Bar-Ness

Third Advisor

David Cooper

Abstract

The complete PC-based hardware design along with the initialization and control software of the JPEG algorithm is presented in this thesis. The hardware could run in real-time to compress, decompress and display still frame images. LSI Logic JPEG chipset was used in the design. This is a dedicated chipset for the JPEG compression algorithm.

A simulation software was used for studying the performance of MPEG video compression algorithm. Various video test sequences were compressed through the codec simulation software and the resulting rate-distortion performance was calculated. These are compared with the performance of JPEG based image sequence compressor.

It is found that the MPEG-based video codec significantly outperforms the JPEG-based codec for the test sequences considered at low to medium bit rates.

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