Document Type


Date of Award


Degree Name

Master of Science in Electrical Engineering - (M.S.)


Electrical and Computer Engineering

First Advisor

Yeheskel Bar-Ness

Second Advisor

Joseph Frank

Third Advisor

Zoran Siveski


Many methods have been developed for evaluating the jitter performance of timing recovery circuits for binary synchronous transmission systems. These circuits consist of a nonlinear device followed by a narrowband filter tuned to the pulse repetition frequency. This thesis introduce delay shifts in the timing recovery circuits to improve the jitter performance. The function of the delay shifts is analyzed and mathematical proof of jitter performance improvement is given for the system using square-law device. Finally, the numerical results obtained from the specific examples serve to illustrate the significant improvement between the system with and without delay shifts. That is, one delay shift introduced in the system can gain nearly 3 db in rms jitter performance.



To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.