Date of Award

Spring 1980

Document Type

Thesis

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical Engineering

First Advisor

Robert De Lucia

Second Advisor

Joseph J. Strano

Third Advisor

W. H. Warren Ball

Abstract

It is the intent of this thesis to acquaint the reader with a tool which is available for use in the digital circuit design field. The reader is now able to totally simulate via DLS the digital logic design he creates on paper before it ever takes a hardware form. The computer program accepts a detailed description of the schematic and creates timing diagrams, loading statistics, cross references, and various lists for future documentation.

The user needs no programming knowledge and will find the requirements to run a simulation with DLS extremely user oriented. The simulation descriptions and command language are tailored to logic design applications. The format is straight forward, utilizing standard English language and logic design concepts. To code a design for simulation the designer needs only a well labeled circuit diagram, where all the inputs and outputs of each element has a label With the addition of a few simulation parameters DLS will take the network description and form a program in memory which will recreate the operations of the digital circuit.

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