Document Type
Thesis
Date of Award
Spring 1996
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
William N. Carr
Second Advisor
Siu Bor Lau
Third Advisor
Kenneth Sohn
Abstract
This thesis describes the design, implementation and test for a new CMOS analog-to-digital converter IC chip. In designing the analog-to-digital converter in this thesis a radically different comparator design that is only available with CMOS logic. The design utilizes a single CMOS inverter as an ultra-high gain amplifier. This approach reduces the circuit dependence upon matching of the transistors similar to the traditional method. This new design requires less area since the comparator utilizes fewer transistors.
Flash analog-to-digital converters use 2" - 1 comparators to do a single conversion where n is the number of bits used. These comparators are traditionally made with differential transistor amplifiers in order to obtain matched characteristics. Effects of mismatch in current gains and base emitter voltage is reduced in the new design since the amplifier topology does not depend entirely upon perfectly matched transistors.
Recommended Citation
Levinson, Joseph E., "Flash ADC using 2μm CMOS P-well technology : design and test" (1996). Theses. 1099.
https://digitalcommons.njit.edu/theses/1099
