Pipelined implementation of fixed point square root in FPGA using modified non-restoring algorithm

Document Type

Conference Proceeding

Publication Date

5-28-2010

Abstract

Square root is one of the fundamental arithmetic operations in signal and image processing algorithms. This article presents a novel pipelined architecture to implement N-bits fixed point square root in FPGA using non-restoring algorithm. Pipelining hazards were avoided by modifying the non-restoring algorithm resulting in a 30% improved latency time. Furthermore, the proposed architecture is flexible and can be modified as per the need of an application. The performance of the proposed system, as a function of execution time and power consumption per operation, has been compared with other floating point pipelined implementations. It is demonstrated that the proposed system is ∼ 2 times efficient compared to its counterparts. ©2010 IEEE.

Identifier

77952616816 (Scopus)

ISBN

[9781424455850]

Publication Title

2010 the 2nd International Conference on Computer and Automation Engineering Iccae 2010

External Full Text Location

https://doi.org/10.1109/ICCAE.2010.5452039

First Page

226

Last Page

230

Volume

3

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