An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays

Document Type

Conference Proceeding

Publication Date

3-1-2020

Abstract

In this work, we present a scheme for implementing learning on a digital non-volatile memory (NVM) based hardware accelerator for Spiking Neural Networks (SNNs). Our design estimates across three prominent non-volatile memories - Phase Change Memory (PCM), Resistive RAM (RRAM), and Spin Transfer Torque RAM (STT-RAM) show that the STT-RAM arrays enable at least 2× higher throughput compared to the other two memory technologies. We discuss the design and the signal communication framework through the STT-RAM crossbar array for training and inference in SNNs. Each STT-RAM cell in the array stores a single bit value. Our neurosynaptic computational core consists of the memory crossbar array and its read/write peripheral circuitry and the digital logic for the spiking neurons, weight update computations, spike router, and decoder for incoming spike packets. Our STT-RAM based design shows ~20× higher performance per unit Watt per unit area compared to conventional SRAM based design, making it a promising learning platform for realizing systems with significant area and power limitations.

Identifier

85087411502 (Scopus)

ISBN

[9783981926347]

Publication Title

Proceedings of the 2020 Design Automation and Test in Europe Conference and Exhibition Date 2020

External Full Text Location

https://doi.org/10.23919/DATE48585.2020.9116226

First Page

1019

Last Page

1024

Fund Ref

Semiconductor Research Corporation

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