Power-constrained DFT algorithms for non-scan BIST-able RTL data paths

Authors

Zhiqiang You, Nara Institute of Science and Technology
Ken'ichi Yamaguchi, National Institute of Technology, Nara College
Michiko Inoue, Nara Institute of Science and Technology
Jacob Savir, Newark College of Engineering
Hideo Fujiwara, Nara Institute of Science and Technology

Document Type

Conference Proceeding

Publication Date

12-1-2004

Abstract

This paper proposes two power-constrained test synthesis schemes and scheduling algorithms, under non-scan BIST, for RTL data paths. The first scheme uses boundary non-scan BIST, and can achieve a low hardware overhead. The second scheme uses generic non-scan BIST, and can offer some tradeoffs between hardware overhead, test application time and power dissipation. A designer can easily select an appropriate design parameter based on the desired tradeoff. Experimental results confirm good performance and practicality of our new approaches.

Identifier

13244299007 (Scopus)

Publication Title

Proceedings of the Asian Test Symposium

ISSN

10817735

First Page

32

Last Page

39

Recommended Citation

You, Zhiqiang; Yamaguchi, Ken'ichi; Inoue, Michiko; Savir, Jacob; and Fujiwara, Hideo, "Power-constrained DFT algorithms for non-scan BIST-able RTL data paths" (2004). Faculty Publications. 20127.
https://digitalcommons.njit.edu/fac_pubs/20127