Integration of high-K dielectrics into sub-65nm CMOS technology: Requirements and challenges

Document Type

Conference Proceeding

Publication Date

12-1-2004

Abstract

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10 nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. In this paper some of the on-going research work on charge trapping will be reviewed. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO 2 and HfSiO 2 will be focused. ©2004IEEE.

Identifier

27944462684 (Scopus)

Publication Title

IEEE Region 10 Annual International Conference Proceedings TENCON

First Page

D320

Last Page

D323

Volume

D

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