Resource-driven optimizations for transient-fault detecting superscalar microarchitectures

Document Type

Conference Proceeding

Publication Date

1-1-2005

Abstract

Increasing microprocessor vulnerability to soft errors induced by neutron and alpha particle strikes prevents aggressive scaling and integration of transistors in future technologies if left unaddressed. Previously proposed instruction-level redundant execution, as a means of detecting errors, suffers from a severe performance loss due to the resource shortage caused by the large number of redundant instructions injected into the superscalar core. In this paper, we propose to apply three architectural enhancements, namely 1) floating-point unit sharing (FUS), 2) prioritizing primary instructions (PRI), and 3) early retiring of redundant instructions (ERT), that enable transient-fault detecting redundant execution in superscalar microarchitectures with a much smaller performance penalty, while maintaining the original full coverage of soft errors. In addition, our enhancements are compatible with many other proposed techniques, allowing for further performance improvement. © Springer-Verlag Berlin Heidelberg 2005.

Identifier

33646499628 (Scopus)

ISBN

[3540296433, 9783540296430]

Publication Title

Lecture Notes in Computer Science Including Subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics

External Full Text Location

https://doi.org/10.1007/11572961_17

e-ISSN

16113349

ISSN

03029743

First Page

200

Last Page

214

Volume

3740 LNCS

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