Implementation of generalized DFT on Field Programmable Gate Array

Document Type

Conference Proceeding

Publication Date

10-23-2012

Abstract

We introduce the implementation of Generalized Discrete Fourier Transform (GDFT) with nonlinear phase on a Field Programmable Gate Array (FPGA.) After briefly revisiting the GDFT framework, we apply the framework to a channel equalization problem in an Orthogonal Frequency Division Multiplexing (OFDM) communication system. The block diagram of the system is introduced and detailed explanations of the implementation for each block are given along with the necessary VHDL code snippets. The resource usage and registered performance of the design is reported and alternatives to improve the design in terms of performance and resolution are provided. To the best of our knowledge, this is the first hardware implementation of GDFT reported in the literature. © 2012 IEEE.

Identifier

84867625956 (Scopus)

ISBN

[9781467300469]

Publication Title

ICASSP IEEE International Conference on Acoustics Speech and Signal Processing Proceedings

External Full Text Location

https://doi.org/10.1109/ICASSP.2012.6288227

ISSN

15206149

First Page

1709

Last Page

1712

This document is currently not available here.

Share

COinS