Random pattern testability of memory control logic

Document Type

Conference Proceeding

Publication Date

1-1-1997

Abstract

This paper analyzes the random pattern testability of faults in the control logic of an embedded memory. We show how to compute exposure probabilities of these faults using mostly signal probability computations. We also show that the hardest memory control logic fault to detect is not necessarily the one with the lowest detection probability at the memory boundary.

Identifier

0030644738 (Scopus)

Publication Title

Proceedings of the IEEE VLSI Test Symposium

First Page

399

Last Page

407

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