Versatile processor design for efficiency and high performance

Document Type

Conference Proceeding

Publication Date

1-1-2000

Abstract

New architectural concepts are introduced for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2-CPU (Data-Driven processor) follows the natural flow of programs, minimizes the number of redundant operations, lowers the hardware cost, and reduces the power consumption. Instructions enter the processing unit when they are ready to execute or when all their operand(s) are to be available within a f a 0 clock cycles. This approach results in outstanding pedormance and elimination of large numbers of redundant operations that plague current processor designs. A comparative analysis of our design with conventional designsproves that it is capable of better perj6ormunce and higher efficiency.

Identifier

85117695263 (Scopus)

ISBN

[0769509363, 9780769509365]

Publication Title

Proceedings International Symposium on Parallel Architectures Algorithms and Networks I Span 2000

External Full Text Location

https://doi.org/10.1109/ISPAN.2000.900295

First Page

266

Last Page

271

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