RAM BIST
Document Type
Conference Proceeding
Publication Date
1-1-2000
Abstract
A RAM test scheme is described. The scheme can be used in both built-in mode and off-chip/module mode. Fault diagnosis is simple and never subjected to aliasing. Depending upon the test length, many kinds of failures can be detected, including stuck-cells, decoder faults, and shorts. Used in the built-in mode, the scheme does not slow down normal array operation and the hardware overhead is very low.
Identifier
0033722088 (Scopus)
Publication Title
Conference Record IEEE Instrumentation and Measurement Technology Conference
First Page
204
Last Page
211
Volume
1
Recommended Citation
Savir, Jacob, "RAM BIST" (2000). Faculty Publications. 15653.
https://digitalcommons.njit.edu/fac_pubs/15653
