BIST-based fault diagnosis in the presence of embedded memories

Document Type

Article

Publication Date

1-1-2001

Abstract

An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.

Identifier

0035661869 (Scopus)

Publication Title

VLSI Design

External Full Text Location

https://doi.org/10.1155/2001/32515

ISSN

1065514X

First Page

487

Last Page

500

Issue

4

Volume

12

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