Single-clock, single-latch, scan design

Document Type

Conference Proceeding

Publication Date

1-1-2002

Abstract

This paper describes a new scan design that uses the same clock for both scan and functional mode. A test mode signal distinguishes between normal and test operations. This new design enjoys savings in circuits, pins, test time, and also enjoys the benefits of a high-speed scan capability.

Identifier

0036047837 (Scopus)

Publication Title

Conference Record IEEE Instrumentation and Measurement Technology Conference

First Page

613

Last Page

615

Volume

1

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