Negative bias temperature instability in TIN/Hf-silicate based gate stacks

Document Type

Conference Proceeding

Publication Date

1-1-2007

Abstract

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSixOy (20% SiO 2) based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (△VT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of △V T in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si-H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/Si interface probably limits the interface state generation and △VT they quickly reach saturation. © World Scientific Publishing Company.

Identifier

34547478772 (Scopus)

Publication Title

International Journal of High Speed Electronics and Systems

External Full Text Location

https://doi.org/10.1142/s0129156407004345

ISSN

01291564

First Page

127

Last Page

141

Issue

1

Volume

17

This document is currently not available here.

Share

COinS