Low-power multiplierless DCT for image/video coders

Document Type

Conference Proceeding

Publication Date

10-27-2009

Abstract

A multiplierless discrete cosine transform (DCT) architecture is proposed to improve the power efficiency of image/video coders. Power reduction is achieved by minimizing both the number of arithmetic operations and their bit width. To minimize arithmetic-operation redundancy, our DCT design focuses on Chen's factorization approach and the constant matrix multiplication (CMM) problem. The 8x1 DCT is decomposed using six two-input butterfly networks. Each butterfly is for 2x2 matrix multiplication and requires a maximum of eight adders/subtractors with 13-bit cosine coefficients. Consequently, the proposed 8x1 DCT architecture is composed of 56 adders and subtractors, which represent a reduction of 61.9% and 46.1% in arithmetic operations compared to the conventional NEDA and CORDIC architectures, respectively. To further improve the power efficiency, an adaptive companding scheme is proposed. The proposed DCT architecture was implemented on a Xilinx FPGA. The results from power estimation show that our architecture can reduce the power dissipation by up to 90% compared to conventional multiplierless DCT architectures. ©2009 IEEE.

Identifier

70350245007 (Scopus)

ISBN

[9781424429769]

Publication Title

Digest of Technical Papers IEEE International Conference on Consumer Electronics

External Full Text Location

https://doi.org/10.1109/ISCE.2009.5156873

ISSN

0747668X

First Page

133

Last Page

136

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