Electrical characterization of dry and wet processed interface layer in Ge/High-K devices

Document Type

Article

Publication Date

3-1-2016

Abstract

In this work, the dry and wet processed interface layers for three different p type Ge/atomic layer deposition (ALD) 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN gate stacks on 300 mm wafers were studied at low temperatures by capacitance-voltage (CV), conductance-voltage measurement, and deep level transient spectroscopy. The interface treatments were (1) simple chemical oxidation (Chemox); (2) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR and SPAOx); and (3) COR followed by vapor O3 treatment (COR and O3). Since low temperature measurements are more reliable, several parameters like equivalent oxide thickness, flatband voltage, bulk doping, and surface potential as a function of gate voltage are reported. Different temperature CV measurement suggests that all the samples are pinned at flat band voltage (Cit give a pseudoaccumulation region) due to large Dit (larger than 1013cm-2/eV). Room temperature measurement indicates that superior results were observed for slot-plane-plasma-oxidation processed samples.

Identifier

84960917076 (Scopus)

Publication Title

Journal of Vacuum Science and Technology B Nanotechnology and Microelectronics

External Full Text Location

https://doi.org/10.1116/1.4943559

e-ISSN

21662754

ISSN

21662746

Issue

2

Volume

34

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