Power-performance optimization of a virtualized SMT vector processor via thread fusion and lane configuration

Document Type

Conference Proceeding

Publication Date

9-2-2016

Abstract

Lane-based Vector Processors (VPs) are highly scalable. However, they become less energy efficient as they scale for vector applications having insufficient data-level parallelism (DLP) to keep the extra computation lanes fully occupied. We present a scalable and yet flexible VP that is capable of dynamically deactivating some of its computing lanes in order to reduce static power with minimum performance loss. In addition, our simultaneous multi-threaded (SMT) VP can exploit identical instruction flows that may be present in different vector applications by running in a novel fused mode that increases its utilization. We introduce a power model and two optimization policies for minimizing the consumed energy, or the product of the energy and runtime for a given application. Benchmarking that involves an FPGA prototype shows up to 33.8% energy reduction in addition to 40% runtime improvement, or up to 62.7% reduction in the product of energy and runtime.

Identifier

84988984785 (Scopus)

ISBN

[9781467390385]

Publication Title

Proceedings of IEEE Computer Society Annual Symposium on VLSI Isvlsi

External Full Text Location

https://doi.org/10.1109/ISVLSI.2016.27

e-ISSN

21593477

ISSN

21593469

First Page

81

Last Page

86

Volume

2016-September

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