Figure 6.18: Internal design of the positive edge-triggered D flip-flop with preset and clear.

Author ORCID Identifier

0000-0003-3621-0168

Authors

John D. Carpinelli, New Jersey Institute of TechnologyFollow

Document Type

Animation

Publication Date

6-26-2023

Description

Figure 6.18: Internal design of the positive edge-triggered D flip-flop with preset and clear. There are six 3-input NAND gates. The first has inputs PRE', the output of the second NAND gate, and the output of the fourth NAND gate. The seoncd has inputs CLR', the output of the first NAND gate, and CLK. The third NAND gate has inputs CLK, the output of the second NAND gtate, and the output of the fourth NAND gate. The fourth NAND gate has inputs D, CLR', and the output of the third NAND date. The fifth NAND gate has inputs PRE', the output of the second NAND gate, and the output of the sixth NAND gate, and its output is labeled Q. The sixth NAND gate has inputs CLR', the output of the third NAND gate, and the output of the fifth NAND gate, and its output is labeled Q'. Initially, PRE', CLR', CLK, and D are set to 0. The outputs of the six NAND gates are 0, 1, 1, 1, 0, and 1, respectively. Then D is set to 1 and the outputs become 1, 1, 1, 0, 0, and 1. Then CLK becomes 1 and the outputs become 1, 0, 1, 0, 1, and 0. Next, CLK returns to 0 and the outputs become 1, 1, 1, 0, 1, and 0. D is set to 0 and the outputs become 0, 1, 1, 1, 1, and 0. CLK once again becomes 1, and the outputs become 0, 1, 0, 1, 0, and 1. Then PRE' becomes 0 and the gate outputs become 1, 0, 1, 1, 1, and 0. PRE' returns to 1 and the outputs remain unchanged. CLK returns to 0 and the outputs become 0, 1, 1, 1, 1, and 0. Next, CLK is set to 1 and the outputs become 0, 1, 0, 1, 0, and 1. CLK returns to 0 and the outputs become 0, 1, 1, 1, 0, and 1. D become 1 and the outputs become 1, 1, 1, 0, 0, and 1. Then CLK returns to 1 and the outputs become 1, 0, 1, 0, 1, and 0. Next, CLR' is set to 0 and the outputs become 0, 1, 0, 1, 0, and 1. CLR' returns to 1 and the outputs remain unchanged. CLK returns to 0 and the outputs become 1, 1, 1, 0, 0, and 1. CLK becomes 1 and the outputs become 1, 0, 1, 0, 1, and 0.

Recommended Citation

Carpinelli, John D., "Figure 6.18: Internal design of the positive edge-triggered D flip-flop with preset and clear." (2023). An Animated Introduction to Digital Logic Design - Animations. 84.
https://digitalcommons.njit.edu/dld-animations/84

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