Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks

Author

Yi Ming Ding, New Jersey Institute of Technology

Document Type

Dissertation

Date of Award

Summer 8-31-2016

Degree Name

Doctor of Philosophy in Electrical Engineering - (Ph.D.)

Department

Electrical and Computer Engineering

First Advisor

Durgamadhab Misra

Second Advisor

Leonid Tsybeskov

Third Advisor

Marek Sosnowski

Fourth Advisor

Alan E. Delahoy

Fifth Advisor

Purushothaman Srinivasan

Sixth Advisor

Kandabara Tapily

Abstract

The oxide/substrate interface quality and the dielectric quality of metal oxide semiconductor (MOS) gate stack structures are critical to future CMOS technology. As SiO₂ was replaced by the high-k dielectric to further equivalent oxide thickness (EOT), high mobility substrates like Ge have attracted increasing in replacing Si substrate to further enhance devices performance. Precise control of the interface between high-k and the semiconductor substrate is the key of the high performance of future transistor. In this study, traditional electrical characterization methods are used on these novel MOS devices, prepared by advanced atomic layer deposition (ALD) process and with pre and post treatment by plasma generated by slot plane antenna (SPA).

MOS capacitors with a TiN metal gate/3 nm HfAlO/0.5 nm SiO₂/Si stacks were fabricated by different Al concentration, and different post deposition treatments. A simple approach is incorporated to correct the error, introduced by the series resistance (R_s) associated with the substrate and metal contact. The interface state density (D_it), calculated by conductance method, suggests that D_it is dependent on the crystalline structure of hafnium aluminum oxide film. The amorphous structure has the lowest D_it whereas crystallized HfO2 has the highest D_it.

Subsequently, the dry and wet processed interface layers for three different p type Ge/ALD 1nm-Al₂O₃/ALD 3.5nm-ZrO₂/ALD TiN gate stacks are studied at low temperatures by capacitance-voltage (CV),conductance-voltage (GV) measurement and deep level transient spectroscopy (DLTS). Prior to high-k deposition, the interface is treated by three different approaches (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAO_x); and (iii) COR followed by vapor O₃ treatment (COR&O₃). Room temperature measurement indicates that superior results are observed for slot-plane-plasma-oxidation processed samples.

The reliability of TiN/ZrO₂/Al₂O₃/p-Ge gate stacks is studied by time dependent dielectric breakdown (TDDB). High-k dielectric is subjected to the different slot plane antenna oxidation (SPAO) processes, namely, (i) before high-k ALD (Atomic Layer Deposition), (ii) between high-k ALD, and (iii) after high-k ALD. High-k layer and interface states are improved due to the formation of GeO₂ by SPAO when SPAO is processed after high-k. GeO₂ at the interface can be degraded easily by substrate electron injection. When SPAO is processed between high-k layers, a better immunity of interface to degradation was observed under stress.

To further evaluate the high-k dielectrics and how EOT impacts on noise mechanism time zero 1/f noise is characterized on thick and thin oxide FinFET transistors, respectively. The extracted noise models suggest that as a function of temperatures and bias conditions the flicker noise mechanism tends to be carrier number fluctuation model (McWhorter model). Furthermore, the noise mechanism tends to be mobility fluctuation model (Hooge model) when EOT reduces.

Recommended Citation

Ding, Yi Ming, "Electrical characterization of high-k gate dielectrics for advanced CMOS gate stacks" (2016). Dissertations. 83.
https://digitalcommons.njit.edu/dissertations/83