Author ORCID Identifier

0000-0003-3496-6076

Document Type

Dissertation

Date of Award

5-31-2025

Degree Name

Doctor of Philosophy in Computing Sciences - (Ph.D.)

Department

Computer Science

First Advisor

Jing Li

Second Advisor

Vincent Oria

Third Advisor

Przemyslaw Musialski

Fourth Advisor

Shuai Zhang

Fifth Advisor

Xin Zhang

Abstract

This dissertation presents a comprehensive automated framework for power converter design, leveraging reinforcement learning (RL) and graph-transformer networks (GTN) to address critical inefficiencies in traditional manual topology optimization. Motivated by the combinatorial increase of circuit design spaces and the computational cost of iterative simulations, this work develops a robust framework for generating energy-efficient topologies requiring rapid and reliable circuit design.

The framework integrates three key components: (1) an upper-confidence-bound-tree-based (UCT-based) RL model for circuit topology space exploration, (2) parallelized UCT algorithms to accelerate exploration processes, (3) a Graph-Transformer-based Network enabling fast circuit performance evaluation. Experimental validation demonstrates the whole framework achieves great effectiveness. The UCT-based topology generation achieves 67% faster convergence than baseline methods. The parallelization scheme achieves a 9.7x speedup with little performance loss. Moreover, the GTN model reduces total optimization time by 98.2% when replacing simulations.

This dissertation advances circuit design automation through three innovations: (1) RL-based topology generation default policies with offline data, (2) parallel UCT for distributed circuit topology exploration, and (3) a GTN surrogate model resolving data discontinuity in topology spaces. This research represents a significant advancement in the field of power converter design automation. By combining reinforcement learning, parallel exploration techniques, and a graph-based surrogate model, the highly efficient framework can generate near-optimal circuit topologies with reduced computational costs. The experiment results demonstrate that this approach can accelerate the design process while ensuring high-quality results. Future work includes extending the framework to broader analog circuit classes and integrating active learning for adaptive GTN refinement.

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