Document Type
Dissertation
Date of Award
Spring 5-31-1989
Degree Name
Doctor of Engineering Science in Electrical Engineering
Department
Electrical and Computer Engineering
First Advisor
John D. Carpinelli
Second Advisor
Raj Pratap Misra
Third Advisor
Peter A. Ng
Fourth Advisor
Anthony D. Robbi
Abstract
Interconnection networks represent the backbone of multiprocessor systems. A failure in the network, therefore, could seriously degrade the system performance. For this reason, fault tolerance has been regarded as a major consideration in interconnection network design. This thesis presents two novel techniques to provide fault tolerance capabilities to three major networks: the Baseline network, the Benes network and the Clos network.
First, the Simple Fault Tolerance Technique (SFT) is presented. The SFT technique is in fact the result of merging two widely known interconnection mechanisms: a normal interconnection network and a shared bus. This technique is most suitable for networks with small switches, such as the Baseline network and the Benes network. For the Clos network, whose switches may be large for the SFT, another technique is developed to produce the Fault-Tolerant Clos (FTC) network. In the FTC, one switch is added to each stage. The two techniques are described and thoroughly analyzed.
Recommended Citation
Nassar, Hamed Mohamed, "Fault-tolerant interconnection networks for multiprocessor systems" (1989). Dissertations. 1232.
https://digitalcommons.njit.edu/dissertations/1232
