Document Type
Thesis
Date of Award
5-31-1991
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Durgamadhab Misra
Second Advisor
N. M. Ravindra
Third Advisor
Kenneth Sohn
Abstract
A new C-MOS NAND and CMOS full adder logic circuits which reduces hot carrier problems are discussed. The application of new circuit lowers the channel electric field in N-MOSFET during switching transient and leads to suppression of the N-MOSFET substrate current. The simulation results shows that about 3.99 and 3.75 times smaller peak substrate current are obtained in C-MOS NAND and adder with new circuit compared to the conventional logic circuits. These logic circuits also gives better noise and shows shorter rise and fall times. The new concept provides highly reliable logic circuits without any change of device structure or fabrication process.
Recommended Citation
Jaswal, Tejinder K., "A CMOS logic circuit to reduce substrate current/hot carrier effect" (1991). Theses. 2511.
https://digitalcommons.njit.edu/theses/2511
