Document Type
Thesis
Date of Award
12-31-1990
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Wei Chen
Second Advisor
Durgamadhab Misra
Third Advisor
N. M. Ravindra
Abstract
Delay information of a circuit is often used in the areas of timing verification, timing analysis, race detection and circuit optimization. Given a circuit its delay can be estimated by various simulation techniques. SPICE is one of the simulation techniques, but it is seen that with the increase in the complexity of the circuit the SPICE circuit simulation technique to obtain delay information become cumbersome and computationally too expensive. So as to overcome the above disadvantages of the circuit simulation technique to obtain delay information various timing delay models were developed. However general survey of most of these timing delay model show that they suffer from the problem of accuracy while estimating the delay of a given circuit.
The previous model used to work with linear RC-approach method treating the transistor as a device represented by a fixed resistance and capacitance with a scale factor, without considering the effect of input waveform and non-linearities of MOS on delay. The error in delay estimation is roughly ranging from 30% to 40%.
The main objective of the thesis is to develop a timing delay model which has higher accuracy and precisely resembles the circuit simulation techniques. The Timing delay model, based on charge conservation principle is used for estimating accurately the delay in a circuit. The basic principle of charge conservation, i.e the time taken by the capacitor to discharge (fall time estimation) and the time taken by the capacitor to charge (rise time estimation).
Recommended Citation
Bisen, Bharatsingh K., "A transistor delay model based on charge conservation" (1990). Theses. 2480.
https://digitalcommons.njit.edu/theses/2480
