Document Type
Thesis
Date of Award
9-30-1988
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
John D. Carpinelli
Second Advisor
Stanley S. Reisman
Abstract
The Motorola 68020 microprocessor, its paged memory management unit MC68851 and cache memories are rigorously studied. The simulation model of this uniprocessor, multiprogramming system was constructed and tested to determine the optimal physical cache size.
The parameters varied in the model are the cache size, the degree of multitasking, the loop count and size, the cache algorithm and the time slice given to every task. A number of simulations have been conducted and the results are examined.
Recommended Citation
Christou, Charalambos Stephanou, "Optimal cache size in microprocessor-based multiprogramming system" (1988). Theses. 3036.
https://digitalcommons.njit.edu/theses/3036
