Document Type

Thesis

Date of Award

9-30-1990

Degree Name

Master of Science in Electrical Engineering - (M.S.)

Department

Electrical and Computer Engineering

First Advisor

N. M. Ravindra

Second Advisor

Kenneth Sohn

Third Advisor

Durgamadhab Misra

Abstract

In recent years, investigations on polysilicon grain structures have shown that all polysilicon films by LPCVD which are most used in today's integrated circuits are columnar in structure. In this work, a square columnar grain structure has been considered to model electrical properties of polycrystalline silicon films instead of all previous one-dimensional grain structure models. By solving Poisson's equation with certain boundary conditions, we find that the barrier height at the corners of the grain is lower than that in the one-dimensional case. Assuming the trapping state energy level as constant, we also find that this level has a value higher than that in the one-dimensional case. The average carrier concentration in the columnar grain structure is lower than that in the one-dimensional case because both charge-depletion regions in vertical and horizontal to carrier movement direction are to he considered. In our model, we obtain the empirical parameters f and n to be closer to one. f and n are parameters that make theoretical results fit better with experimental data. For a more precise model, f and n are closer to one.

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