Document Type
Thesis
Date of Award
9-30-1990
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical and Computer Engineering
First Advisor
Wei Chen
Second Advisor
Durgamadhab Misra
Third Advisor
Nirwan Ansari
Abstract
Since the early 1960's, semiconductor chips have matured from single transistor devices to one million transistors per chip. The integration has been achieved by reducing transistor dimensions, and by increasing chip sizes. However, physical limits are being reached as submicrometre dimensions are approached. Fault tolerance has to be used to maintain the increase in the chip complexity. Yield improvement is only one of the many possible gains of fault tolerance. The dense integration of logic on a single chip also creates a huge test problem. in recent years a great deal of effort has gone into the development of yield modelling. This work deals with the introduction of a new technique to an "SRANI" called " Built In Self Test" (13IST), and a technique called "Multiple Word / Bit line redundancy" which enhances the yield. The simulation is carried out using a behavioral simulator called "VERILOG". Hardware for "BIST" to implement an algorithm of order 0(1.3N) which finds all possible faults is designed. The faults that can be detected include , stuck at 0 , stuck at 1, transition faults, coupling faults, data retention faults.
Recommended Citation
Rao, Maremanda V. R., "A self testing strategy for the wafer scale hierarchical memory architecture" (1990). Theses. 2910.
https://digitalcommons.njit.edu/theses/2910
