Document Type
Thesis
Date of Award
8-31-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
Constantine N. Manikopoulos
Second Advisor
Nirwan Ansari
Third Advisor
Irving Y. Wang
Abstract
CSMA/CD based Local Area Networks account for about 75% of the installed LAN base today. As these networks are becoming available for high channel bandwidth, it is important to identify the bottlenecks in these networks. As channels are becoming high speed, bottleneck is shifting from channel to protocol processing. This delay depends on a particular implementation of the protocol and not the protocol standard itself.
This Thesis presents the analysis of delay on Ethernet. To achieve realistic results NJIT Ethernet, as it is configured, is modelled and simulated. Traffic on this network is measured and load on each segment is calculated for input to the simulation model. Throughput and delay characteristics are derived and presented. A total packet delay is broken up into two components, channel delay and protocol processing delay. The bottleneck at high loads is identified and results are analysed.
Recommended Citation
Rangwani, Jagdish Gangrimal, "Protocol processing delay analysis on Ethernet by simulation of NJIT Ethernet" (1989). Theses. 2872.
https://digitalcommons.njit.edu/theses/2872
