Document Type
Thesis
Date of Award
5-31-1989
Degree Name
Master of Science in Electrical Engineering - (M.S.)
Department
Electrical Engineering
First Advisor
William N. Carr
Second Advisor
Kenneth Sohn
Third Advisor
N. M. Ravindra
Abstract
This thesis presents the design of a Dynamic CMOS Programmable Logic Device chip (NJIT PLD). The main feature of the chip is its reconfigurability and the provision of a processor interface which makes the chip capable of performing coprocessor like functions. The chip has been designed to be used with the Intel 8088 microprocessor, but may also find stand-alone applications. Provision is made for dynamic reconfiguration of the chip. The configuration data for the chip comes from a serial PROM, to which the chip sends a synchronizing clock. The NJIT PLD is a high performance, digital integrated circuit. It has a regular, flexible, user-programmable array architecture. A 2960 node static memory array is used to store the logic configuration of the chip. All storage nodes are applications programmable by means of a serial bit stream. Provision is made for power-up initialization. The logic architecture of the chip consists of 4 Programmable Logic Arrays (PLAs) interconnected by means of an 8-bit user routable databus. Each PLA has 8 inputs, 20 product terms and 8 outputs, in addition to 4 registered feedback terms which enables sequential operations. Each PLA is implemented as a NOR-NOR structure. Parallel operations in the 4 PLAs is a strong feature of the chip. Data can be routed to any PLA by performing processor I/O operations. The 26-pin chip has been designed using 3 micron CMOS technology and has an area of 91.5 sq mm. It is designed to work at clock rates up to 14.7 MHz and is expected to find applications in signal processing and in hardware accelerators.
Recommended Citation
Parvathala, Praveen K., "A dynamic CMOS programmable logic device" (1989). Theses. 2860.
https://digitalcommons.njit.edu/theses/2860
